[Bug c/112433] New: RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

            Bug ID: 112433
           Summary: RISC-V GCC-15 feature: Split register allocation into
                    RVV and non-RVV, and make vsetvl PASS run between them
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

It's inspired by recent LLVM patch:
https://github.com/llvm/llvm-project/pull/70549

Consider this following situation (before RA):

p1: def r136
p2: vadd.vv (use r136)
p3: vadd.vv (use r136)

note r136 is AVL.

We currently run VSETVL PASS after RA which makes r136 register live range
from p1 to p3.

However, if we are able to split RVV and non-RVV register allocation as
follows:

PASS 1: allocate only RVV registers.
PASS 2: VSETVL PASS.
PASS 3: allocate all non-RVV registers.

Then after VSETVL PASS, we will end up with:

p1: def r136
p2: vsetvl zero, r136
p3: vadd.vv (use none)
p4: vadd.vv (use none)

Then r136 live range will be shorten from p1 to p2.

It should be easily addressed since RVV is different REG_CLASS.

This feature is going to be supported by Lehua in GCC-15.