[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[kito at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #4 from Kito Cheng <kito at gcc dot gnu.org> ---
Yeah, 3 major goal in LLVM is improving scheduling, partial spilling and
re-materialization, but none of those points are issue for RISC-V GCC :P

Ref:
https://docs.google.com/presentation/d/1BOYNYKe1T-u3Q5HXRrcObLUkdKSPASmnuQTkALvJXto/edit