https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111768
--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> --- I checked Alderlake's L1 cachesize and it is indeed 48, and L1 cachesize in alderlake_cost is set to 32. But then again, we have a lot of different platforms that share the same cost and they may have different L1 cachesizes, but from a micro-architecture tuning point of view, it doesn't make a difference. A separate cost if only the L1 cachesize is different is quite unnecessary（the size itself is just a parameter for the software prefetch, it doesn't have to be real hardware cachesize)
