https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535
--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kito Cheng <k...@gcc.gnu.org>: https://gcc.gnu.org/g:a2d12abedc89a9439fd6aadc38730fdadca0684f commit r14-113-ga2d12abedc89a9439fd6aadc38730fdadca0684f Author: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> Date: Wed Apr 19 18:41:51 2023 +0800 RISC-V: Fix wrong check of register occurrences [PR109535] count_occurrences will conly count same RTX (same code and same mode), but what we want to track is the occurrence of a register, a register might appeared in the insn with different mode or contain in SUBREG. Testcase coming from Kito. gcc/ChangeLog: PR target/109535 * config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function. (pass_vsetvl::cleanup_insns): Fix bug. gcc/testsuite/ChangeLog: PR target/109535 * g++.target/riscv/rvv/base/pr109535.C: New test. * gcc.target/riscv/rvv/base/pr109535.c: New test. Signed-off-by: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> Co-authored-by: kito-cheng <kito.ch...@sifive.com>
