https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108874
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Last reconfirmed| |2023-02-23
Target|arm |arm, aarch64
Keywords|needs-bisection |
Status|UNCONFIRMED |NEW
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
How it worked before because of the following combine, removing 1 instruction
and then doing the 4->1 matching:
Trying 7 -> 10:
(set (reg:SI 80 [ D.3188 ])
(ior:SI (lshiftrt:SI (reg:SI 81 [ D.3187 ])
(const_int 8 [0x8]))
(reg:SI 84 [ D.3187 ])))
So we could match add a pattern/split that matching this combine:
Trying 6, 7 -> 10:
6: r99:SI=r97:SI 0>>0x8
7: r100:SI=r99:SI&0xff00ff
REG_DEAD r99:SI
10: r98:SI=r100:SI|r102:SI
REG_DEAD r102:SI
REG_DEAD r100:SI
Failed to match this instruction:
(set (reg:SI 98)
(ior:SI (and:SI (lshiftrt:SI (reg/v:SI 97 [ x ])
(const_int 8 [0x8]))
(const_int 16711935 [0xff00ff]))
(reg:SI 102)))
into two, pushing the and before the shift right.
Note this would require modifying both the arm and aarch64 backends but it
seems doable.
