https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107674
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Andre Simoes Dias Vieira <avie...@gcc.gnu.org>: https://gcc.gnu.org/g:d45ec8a732f449647afa89e46b80a4e0614ec28d commit r13-5647-gd45ec8a732f449647afa89e46b80a4e0614ec28d Author: Andre Vieira <andre.simoesdiasvie...@arm.com> Date: Thu Feb 2 10:01:13 2023 +0000 arm: Remove unnecessary zero-extending of MVE predicates before use [PR 107674] This patch teaches GCC that zero-extending a MVE predicate from 16-bits to 32-bits and then only using 16-bits is a no-op. It does so in two steps: - it lets gcc know that it can access any MVE predicate mode using any other MVE predicate mode without needing to copy it, using the TARGET_MODES_TIEABLE_P hook, - it teaches simplify_subreg to optimize a subreg with a vector outermode, by replacing this outermode with a same-sized integer mode and trying the avalailable optimizations, then if successful it surrounds the result with a subreg casting it back to the original vector outermode. gcc/ChangeLog: PR target/107674 * config/arm/arm.cc (arm_hard_regno_mode_ok): Use new MACRO. (arm_modes_tieable_p): Make MVE predicate modes tieable. * config/arm/arm.h (VALID_MVE_PRED_MODE): New define. * simplify-rtx.cc (simplify_context::simplify_subreg): Teach simplify_subreg to simplify subregs where the outermode is not scalar. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/mve_vpt.c: Change to remove unecessary zero-extend.
