https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108086
--- Comment #16 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> --- (In reply to Richard Biener from comment #13) > (In reply to Richard Biener from comment #12) > > A regression from GCC 10 which compiles this in 90s at -O1. > > > > Richard? Can you please look at this special-case of BB0 insn_info? > > The following might be one way to "fix" it (until we do a bigger testcase) > > diff --git a/gcc/rtl-ssa/insns.h b/gcc/rtl-ssa/insns.h > index f7215972845..b0144f258b2 100644 > --- a/gcc/rtl-ssa/insns.h > +++ b/gcc/rtl-ssa/insns.h > @@ -403,8 +403,7 @@ private: > // MAX_RECOG_OPERANDS is the maximum number of pseudos that can be > // defined by an instruction, so the number of definitions should fit > // easily in 16 bits. > - unsigned int m_num_uses; > - unsigned int m_num_defs : 16; > + unsigned int m_num_uses : 24; The problem is that: // The number of definitions and the number uses. FIRST_PSEUDO_REGISTER + 1 // is the maximum number of accesses to hard registers and memory, and // MAX_RECOG_OPERANDS is the maximum number of pseudos that can be // defined by an instruction, so the number of definitions should fit // easily in 16 bits. holds for real instructions, but not for artificial instructions. Since we don't have any new justification for a limit less than 32 bits, I think we'll just have to grow the structure.
