https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85697
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |missed-optimization
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-05-09
CC| |jakub at gcc dot gnu.org
Component|target |tree-optimization
Ever confirmed|0 |1
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
vectorization is not enabled at -Os (or at -O2), the SSE instructions are
generated by basic-block vectorization though I could imagine that
store-merging
could also generate those from
<bb 2> [100.00%]:
MEM[(struct &)&a] ={v} {CLOBBER};
MEM[(int *)&a] = 0;
MEM[(int *)&a + 8B] = 0;
UseA (&a);
_3 = a.a;
a ={v} {CLOBBER};
return _3;
The target would need to decide whether TImode stores are wanted or not
(via MAX_MOVE_PIECES or sth related). We could also, for -Os and some
embedded targets, consider emitting a memset from store-merging in case
regions are large enough and the initializer is memset compatible.
Similarly a MEM = {} could be used for zeroing, leaving actual implementation
to RTL expansion. What type to use here needs experimentation of course.
