https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |jakub at gcc dot gnu.org,
| |rsandifo at gcc dot gnu.org
Target Milestone|--- |8.0
--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r253337, most likely just latent before.
Either the insns which can't accept 0 immediate for shift should be emitted as
register moves if the shift count is const0_rtx, or we need to use different
constraints for this shift count immediates that don't allow zero.
Right now e.g. the *aarch64_ashr_sisd_or_int_si3 define_insn uses Uss and Usd
constraints for the immediate, which are fine for asr instruction, but not
sshr.
So perhaps add US{s,d} constraints which would be like Us{s,d}, but wouldn't
accept 0?
Relying on GIMPLE passes and/or combiner to always optimize away shifts by 0
doesn't really work.
