https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85512
Bug ID: 85512
Summary: [8 Regression] gcc generating non-existing sshr with
immh == 0
Product: gcc
Version: 8.0.1
Status: UNCONFIRMED
Keywords: assemble-failure
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: zsojka at seznam dot cz
Target Milestone: ---
Host: x86_64-pc-linux-gnu
Target: aarch64-unknown-linux-gnu
Created attachment 44013
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=44013&action=edit
reduced testcase
Output:
$ aarch64-unknown-linux-gnu-gcc -O -fno-if-conversion -c testcase.c
/tmp/ccD6tbg5.s: Assembler messages:
/tmp/ccD6tbg5.s:42: Error: immediate value out of range 1 to 64 at operand 3 --
`sshr v8.2s,v0.2s,0'
According to "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture
profile", the only valid values are:
...
<T> Is an arrangement specifier, encoded in the "immh:Q" field. It can have the
following values:
...
2S when immh = 01xx, Q = 0
...
Shift by 0 is not possible and such encoding would be a very different
instruction.
$ aarch64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-aarch64/bin/aarch64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-259559-checking-yes-rtl-df-extra-aarch64/bin/../libexec/gcc/aarch64-unknown-linux-gnu/8.0.1/lto-wrapper
Target: aarch64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl
--with-sysroot=/usr/aarch64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=aarch64-unknown-linux-gnu
--with-ld=/usr/bin/aarch64-unknown-linux-gnu-ld
--with-as=/usr/bin/aarch64-unknown-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-259559-checking-yes-rtl-df-extra-aarch64
Thread model: posix
gcc version 8.0.1 20180423 (experimental) (GCC)
