https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82518
--- Comment #22 from Richard Earnshaw <rearnsha at gcc dot gnu.org> --- (In reply to Nick Clifton from comment #21) > Hi Aldy, > > >>> instruction. :-( Looking at the code in Handle_Store_Double() in > >>> sim/arm/armemu.c, I think that the reason is probably because the address > >>> for the store is not double word aligned. Which leads me to wonder, > >>> what value is stored in r5 when the STRD instruction is being executed ? > > > >> => 0x8c24 <initialise_monitor_handles+156>: strd r2, [r5, #12] > >> (gdb) info reg r5 > >> r5 0x1b6e8 112360 > > >> ...which is 64 bit aligned. > > But, as you have just discovered, (r5 + 12) is not 64-bit aligned... But from ARMv7 onwards it only has to be 4-byte aligned, which it is. And this code was build for cortex-a9, which is ARMv7-a.
