[Bug target/79912] [7 regression] LRA unable to generate reloads after r245655

[npickito at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79912

--- Comment #8 from Kito Cheng <npickito at gmail dot com> ---
Hi Matthew:
Oh, my fault, I just go another way[1] to fix this issue, but I got worse code
gen for both hard-float and soft-float after r245655, before.*.s is generate by
gcc with revert r245655, *rv32imafd.s for hard-float and *rv32ima.s for
soft-float, RISC-V define WORD_REGISTER_OPERATIONS as 1, but also provide qi/hi
load/store, I guess this may effect other RISC arch too.

$ diff before.rv32imafd.s after.rv32imafd.s
139c139,142
<       lbu     a5,-244(s0)
---
>       flw     fa5,-244(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5
141c144,147
<       lbu     a5,-248(s0)
---
>       flw     fa5,-248(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5
143c149,152
<       lbu     a5,-252(s0)
---
>       flw     fa5,-252(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5
145c154,157
<       lbu     a5,-256(s0)
---
>       flw     fa5,-256(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5
147c159,162
<       lbu     a5,-260(s0)
---
>       flw     fa5,-260(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5
173c188,191
<       lbu     a5,-264(s0)
---
>       flw     fa5,-264(s0)
>       fmv.x.s a5,fa5
>       fmv.s.x fa5,a5
>       fmv.x.s a5,fa5


$ diff before.rv32ima.s after.rv32ima.s
143c143
<       lbu     a4,-244(s0)
---
>       lw      a4,-244(s0)
145c145
<       lbu     a4,-248(s0)
---
>       lw      a4,-248(s0)
147c147
<       lbu     a4,-252(s0)
---
>       lw      a4,-252(s0)
149c149
<       lbu     a4,-256(s0)
---
>       lw      a4,-256(s0)
151c151
<       lbu     a4,-260(s0)
---
>       lw      a4,-260(s0)
153c153
<       lbu     a4,-264(s0)
---
>       lw      a4,-264(s0)


[1]
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 89567f7..148967b 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3581,10 +3581,6 @@ riscv_hard_regno_mode_ok_p (unsigned int regno, enum
machine_mode mode)
       if (!FP_REG_P (regno + nregs - 1))
        return false;

-      if (GET_MODE_CLASS (mode) != MODE_FLOAT
-         && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
-       return false;
-
       /* Only use callee-saved registers if a potential callee is guaranteed
         to spill the requisite width.  */
       if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG
@@ -3634,7 +3630,7 @@ riscv_class_max_nregs (reg_class_t rclass, enum
machine_mode mode)
 static reg_class_t
 riscv_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
 {
-  return reg_class_subset_p (FP_REGS, rclass) ? FP_REGS :
+  return reg_class_subset_p (FP_REGS, rclass) && TARGET_HARD_FLOAT ? FP_REGS :
         reg_class_subset_p (GR_REGS, rclass) ? GR_REGS :
         rclass;
 }