https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69454
--- Comment #22 from Ilya Enkovich <ienkovich at gcc dot gnu.org> --- (In reply to H.J. Lu from comment #21) > In another word, STV needs 128-bit aligned stack only when it generates > 12-bit vector instructions. STV never generates such instructions. But RA may spill SSE registers and aligned moves are used for that. I actually expected RA to fix-up alignment requirements or even use DI spills/fills (since we never use full register for STV) but it doesn't happen.
