https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68536
amker at gcc dot gnu.org changed:
What |Removed |Added
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CC| |amker at gcc dot gnu.org
--- Comment #3 from amker at gcc dot gnu.org ---
(In reply to Vladimir Makarov from comment #1)
> (In reply to ktkachov from comment #0)
> > I'm trying to add support in arm for the smmlar instruction from ARMv6.
> > The pattern for it looks like this:
> > (define_insn "*mulsidi3siaddsi_round_v6"
> > [(set (match_operand:SI 0 "s_register_operand" "=r")
> > (plus:SI
> > (match_operator:SI 3 "subreg_highpart_operator"
> > [(plus:DI
> > (mult:DI
> > (sign_extend:DI
> > (match_operand:SI 1 "s_register_operand" "%r"))
> > (sign_extend:DI
> > (match_operand:SI 2 "s_register_operand" "r")))
> > (const_int 2147483648))])
> > (match_operand:SI 4 "s_register_operand" "r")))]
> > "TARGET_32BIT && arm_arch6"
> > "smmlar%?\\t%0, %1, %2, %4"
> > [(set_attr "type" "smmla")
> > (set_attr "predicable" "yes")
> > (set_attr "predicable_short_it" "no")]
> > )
> >
>
> When I try to build GCC with this pattern, I have
>
> ‘subreg_highpart_operator’ was not declared in this scope
>
> Could you provide the predicate definition.
Hi Vlad,
I also ran into ICE with lra_emit_add, though it might be another issue. I
have done preliminary investigation, so could you please give some suggestions?
The thread is at https://gcc.gnu.org/ml/gcc-patches/2015-11/msg02446.html
Thanks very much.
