[Bug rtl-optimization/68536] New: LRA ICEs with new arm pattern

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68536

            Bug ID: 68536
           Summary: LRA ICEs with new arm pattern
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ktkachov at gcc dot gnu.org
                CC: vmakarov at redhat dot com
            Blocks: 49526
  Target Milestone: ---
            Target: arm

I'm trying to add support in arm for the smmlar instruction from ARMv6.
The pattern for it looks like this:
(define_insn "*mulsidi3siaddsi_round_v6"
  [(set (match_operand:SI 0 "s_register_operand" "=r")
         (plus:SI
           (match_operator:SI 3 "subreg_highpart_operator"
             [(plus:DI
                (mult:DI
                  (sign_extend:DI
                    (match_operand:SI 1 "s_register_operand" "%r"))
                  (sign_extend:DI
                    (match_operand:SI 2 "s_register_operand" "r")))
                (const_int 2147483648))])
          (match_operand:SI 4 "s_register_operand" "r")))]
  "TARGET_32BIT && arm_arch6"
  "smmlar%?\\t%0, %1, %2, %4"
  [(set_attr "type" "smmla")
   (set_attr "predicable" "yes")
   (set_attr "predicable_short_it" "no")]
)

However, if I add it to arm.md I get the following ICE during register
allocation:
internal compiler error: Segmentation fault
 }
 ^

0xa9a432 crash_signal
        $SRC/gcc/toplev.c:334
0x930f61 lra_emit_add(rtx_def*, rtx_def*, rtx_def*)
        $SRC/gcc/lra.c:389
0x93130b lra_emit_move(rtx_def*, rtx_def*)
        $SRC/gcc/lra.c:495
0x939fc9 insert_move_for_subreg
        $SRC/gcc/lra-constraints.c:1353
0x9416ce simplify_operand_subreg
        $SRC/gcc/lra-constraints.c:1489
0x9416ce curr_insn_transform
        $SRC/gcc/lra-constraints.c:3416
0x94437d lra_constraints(bool)
        $SRC/gcc/lra-constraints.c:4406
0x933d75 lra(_IO_FILE*)
        $SRC/gcc/lra.c:2267
0x8ef845 do_reload
        $SRC/gcc/ira.c:5383
0x8ef845 execute
        $SRC/gcc/ira.c:5554


Just add this pattern to gcc/config/arm.md and try to compile the testcase:
int
smmlar (int a, int b, int c)
{
  return c + (((long long)a * b + 0x80000000) >> 32);
}

with -O2 and -mcpu=cortex-a15 or something
Is there something wrong with the way I defined the pattern/constraints
or is this an LRA bug?


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=49526
[Bug 49526] extra move instruction for smmul