https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #117 from Oleg Endo <olegendo at gcc dot gnu.org> ---
(In reply to Oleg Endo from comment #94)
> Kaz, do you think we can enable LRA by default for GCC 6?
>
> Some early results from the AMS optimization show new R0 spill failures.
> For example, AMS uses @(R0,Rn) address modes more often. Although I still
> would like to try this R0 prealloc pass, I don't know when I will have time
> for that. Enabling LRA might be easier.
So I've tried compiling the CSiBE set with AMS and LRA. The AMS branch still
has some problems, but without LRA CSiBE at least compiles without errors.
With LRA I get a lot of:
ll_rw_blk.i: In function 'generic_plug_device':
ll_rw_blk.i:8464:1: error: unable to find a register to spill
}
^
ll_rw_blk.i:8464:1: error: this is the insn:
(insn 32 74 61 5 (set (mem/j:QI (plus:SI (reg/v/f:SI 170 [ q ])
(reg:SI 283 [272])) [0 q_2(D)->plugged+0 S1 A32])
(reg:QI 0 r0)) ll_rw_blk.i:8462 276 {*movqi}
(expr_list:REG_DEAD (reg:SI 283 [272])
(expr_list:REG_DEAD (reg:QI 0 r0)
(nil))))
ll_rw_blk.i:8464:1: internal compiler error: in assign_by_spills, at
lra-assigns.c:1431
It seems it has trouble rearranging this:
mov.b r0,@(Rm,Rn)
into
mov.b Rx,@(R0,Rn)
