https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #74 from Oleg Endo <olegendo at gcc dot gnu.org> --- (In reply to Kazumoto Kojima from comment #73) > I'm not sure about ARM. The problematic cases I've looked at are > high R0 pressure cases and IRA decided to allocate equiv value > registers to memory as most profitable ones. > It looks that the remained code size inflation came from R0-ness, > very limited base+display addressing, only one index register and > so on. OK, makes sense. > I'll attach the test cases for them to this PR after merge > from trunk and commit current patches. Thanks!
