http://gcc.gnu.org/bugzilla/show_bug.cgi?id=20020
--- Comment #29 from H.J. Lu <hjl.tools at gmail dot com> 2012-08-13 02:17:28
UTC ---
(In reply to comment #28)
> (In reply to comment #27)
> > Please try this patch:
> >
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> > index c4d85b7..6c4c2ce 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -1853,6 +1853,10 @@ do { \
> >
> > /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
> >
> > +/* An integer expression for the size in bits of the largest integer
> > machine
> > + mode that should actually be used. We allow pairs of registers. */
> > +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode :
> > DImode)
> > +
> > /* Define this macro if it is as good or better to call a constant
> > function address than to call an address kept in a register.
>
> That's the patch that I have been using and testing against (ref: comment #9).
>
> I suggested this:
> #define MAX_FIXED_MODE_SIZE targetm.scalar_mode_supported_p (TImode) ? TImode
> :
> DImode
> because it might allow x86 targets with SSE to also target TIMode for 128 bit
> struct's (on the assumption that TImode will be more efficient).
ix86_scalar_mode_supported_p (TImode) returns false for -m32
even when SSE is enabled. You can submit a patch with
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
plus some testcases.
