http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50883
--- Comment #5 from Sebastian Huber <sebastian.hu...@embedded-brains.de>
2011-10-27 15:19:57 UTC ---
If we look at the function f (the function g is similar):
struct s {
int alignment;
unsigned char a;
unsigned char b;
unsigned char c;
unsigned char d;
};
unsigned f(struct s x)
{
return x.a | (x.b << 8) | (x.c << 16) | (x.d << 24);
}
Currently ARM GCC produces this:
f:
sub sp, sp, #8
add r3, sp, #8
stmdb r3, {r0, r1}
ldrb r0, [sp, #6]
ldrb r3, [sp, #5]
lsls r0, r0, #16
ldrb r2, [sp, #4]
orr r0, r0, r3, lsl #8
ldrb r3, [sp, #7]
orrs r0, r0, r2
orr r0, r0, r3, lsl #24
add sp, sp, #8
bx lr
According to the ARM EABI, this structure is passed in registers r0 and r1.
The return value is in r0. This function may be reduced to:
f:
mov r0, r1
bx lr
The PowerPC GCC performs this optimization.
