http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46975
Summary: Replace 32 bit instructions with 16 bit instructions
in thumb2
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: [email protected]
ReportedBy: [email protected]
Compile the following c code with options -march=armv7-a -mthumb -Os
int gzeof (int s)
{
return s == 1;
}
GCC 4.6 generates:
00000000 <gzeof>:
0: f1a0 0301 sub.w r3, r0, #1 // A
4: 4258 negs r0, r3
6: eb40 0003 adc.w r0, r0, r3 // B
a: 4770 bx lr
Notice that instructions A and B are 32 bits, we can change them to subs and
adcs so both will be 16 bits.
The code sequence is generated by the following peephole2
8731 ;; Attempt to improve the sequence generated by the compare_scc splitters
8732 ;; not to use conditional execution.
8733 (define_peephole2
8734 [(set (reg:CC CC_REGNUM)
8735 (compare:CC (match_operand:SI 1 "register_operand" "")
8736 (match_operand:SI 2 "arm_rhs_operand" "")))
8737 (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
8738 (set (match_operand:SI 0 "register_operand" "") (const_int
0)))
8739 (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
8740 (set (match_dup 0) (const_int 1)))
8741 (match_scratch:SI 3 "r")]
8742 "TARGET_32BIT"
8743 [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
8744 (parallel
8745 [(set (reg:CC CC_REGNUM)
8746 (compare:CC (const_int 0) (match_dup 3)))
8747 (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
8748 (set (match_dup 0)
8749 (plus:SI (plus:SI (match_dup 0) (match_dup 3))
8750 (geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
8751
We should change the new instructions to use subs and adcs.
