Compile the following code with options -march=armv7-a -mthumb -Os
int foo(int *p, int i )
{
return( (i < 0 && *p == 1)
|| (i > 0 && *p == 2) );
}
Gcc generates:
foo:
cmp r1, #0
bge .L2
ldr r0, [r0, #0]
cmp r0, #1
ite ne // A
movne r0, #0 // B
moveq r0, #1 // C
b .L3
.L2:
it eq
moveq r0, r1
beq .L3
ldr r0, [r0, #0]
cmp r0, #2
ite ne // D
movne r0, #0 // E
moveq r0, #1 // F
.L3:
bx lr
Instructions ABC are same as DEF, ideally ABC can be removed and generates
following code:
foo:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
cmp r1, #0
bge .L2
ldr r0, [r0, #0]
cmp r0, #1
b .L3
.L2:
it eq
moveq r0, r1
beq .L3
ldr r0, [r0, #0]
cmp r0, #2
.L3:
ite ne
movne r0, #0
moveq r0, #1
bx lr
This should be handled by try_crossjump_bb. But a single rtl insn is used to
represent the compare and following IT block, like following. So they looks
different.
(insn:TI 24 22 26 src/t1.c:3 (parallel [
(set (reg:SI 0 r0 [orig:133 D.2006 ] [133])
(eq:SI (reg:SI 0 r0 [145])
(const_int 2 [0x2])))
(clobber (reg:CC 24 cc))
]) 682 {*thumb2_compare_scc} (expr_list:REG_UNUSED (reg:CC 24 cc)
(nil)))
(insn:TI 13 11 70 src/t1.c:3 (parallel [
(set (reg:SI 0 r0 [orig:133 D.2006 ] [133])
(eq:SI (reg:SI 0 r0 [142])
(const_int 1 [0x1])))
(clobber (reg:CC 24 cc))
]) 682 {*thumb2_compare_scc} (expr_list:REG_UNUSED (reg:CC 24 cc)
(nil)))
Can we break this insn into two separate ones, one is compare insn to set the
cc register, the other is the IT block?
--
Summary: Missed merging common code sequence at the end of two
basic blocks
Product: gcc
Version: 4.5.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: carrot at google dot com
GCC build triplet: i686-linux
GCC host triplet: i686-linux
GCC target triplet: arm-eabi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42835
