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commit 48369f6cf258b6dcd1d0ce94b92397eba9464393 Author: Niklas Haas <[email protected]> AuthorDate: Thu Mar 5 13:18:40 2026 +0100 Commit: Niklas Haas <[email protected]> CommitDate: Sat Mar 28 18:50:14 2026 +0100 swscale/x86/ops: reserve one more temporary register Slightly more convenient for the calculations inside the filter kernel, and ultimately not significant due to the fact that the extra register only needs to be saved on the loop entrypoint. Sponsored-by: Sovereign Tech Fund Signed-off-by: Niklas Haas <[email protected]> --- libswscale/x86/ops_common.asm | 19 +++++++++++-------- libswscale/x86/ops_int.asm | 2 +- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/libswscale/x86/ops_common.asm b/libswscale/x86/ops_common.asm index 8e4ea6e977..b8fd78c9b6 100644 --- a/libswscale/x86/ops_common.asm +++ b/libswscale/x86/ops_common.asm @@ -247,23 +247,26 @@ endstruc ; Extra registers for free use by kernels, not saved between ops %define tmp0q r4q %define tmp1q r5q +%define tmp2q r6q %define tmp0d r4d %define tmp1d r5d +%define tmp2d r6d %define tmp0w r4w %define tmp1w r5w +%define tmp2w r6w ; Registers for plane pointers; put at the end (and in ascending plane order) ; so that we can avoid reserving them when not necessary -%define out0q r6q -%define in0q r7q -%define out1q r8q -%define in1q r9q -%define out2q r10q -%define in2q r11q -%define out3q r12q -%define in3q r13q +%define out0q r7q +%define in0q r8q +%define out1q r9q +%define in1q r10q +%define out2q r11q +%define in2q r12q +%define out3q r13q +%define in3q r14q ;--------------------------------------------------------- ; Common macros for linking together different kernels diff --git a/libswscale/x86/ops_int.asm b/libswscale/x86/ops_int.asm index bc9e43a098..61ade4cf7f 100644 --- a/libswscale/x86/ops_int.asm +++ b/libswscale/x86/ops_int.asm @@ -61,7 +61,7 @@ SECTION .text ; Global entry point. See `ops_common.asm` for info. %macro process_fn 1 ; number of planes -cglobal sws_process%1_x86, 6, 6 + 2 * %1, 16 +cglobal sws_process%1_x86, 6, 7 + 2 * %1, 16 ; Args: ; execq, implq, bxd, yd as defined in ops_common.int ; bx_end and y_end are initially in tmp0d / tmp1d _______________________________________________ ffmpeg-cvslog mailing list -- [email protected] To unsubscribe send an email to [email protected]
