> For example, there are two copies of register aperture one with low-endian > translation and one with big-endian.
That isn't necessary. I don't think there is overhead using the endian-swapping versions of load & store instructions, and you need specific macros anyways since you absolutely need the proper memory barrier (eieio) on ppc. In fact, with DMA, you technically need more than eieio to synchronize cacheable and non-cacheable accesses on PPC, but since we only DMA from AGP and AGP is mapped non-cacheable, this is currently a non-issue. Ben. ------------------------------------------------------- The SF.Net email is sponsored by: Beat the post-holiday blues Get a FREE limited edition SourceForge.net t-shirt from ThinkGeek. It's fun and FREE -- well, almost....http://www.thinkgeek.com/sfshirt -- _______________________________________________ Dri-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-devel
