On Sun, 2003-09-28 at 21:57, Jacek Rosik wrote: > W liście z nie, 28-09-2003, godz. 20:24, Keith Whitwell pisze: > > Jacek Rosik wrote: > > > > > > 1) About CP. As I understand it it's some kind of queue for commands. > > > So, is there such posibility that if I write some value into register > > > using it and after that another value is written using RADEON_WRITE the > > > second value will be overwritten by first one?
Yes. > > > Is it flushed on context change? For example when server grabs a lock > > > after client. Not necessarily AFAIK; gratuitous flushing of the CP ring could affect performance. > > If you want to write registers in the hardware while the CP is active, it's > > typically necessary to use CP commands to do so. However, it does depend > > which register you are talking about. > > RADEON_CRTC_OFFSET/RADEON_CRTC2_OFFSET in order to flip buffers. Those aren't FIFO'd AFAIK, so writing to them directly should be safe even while the CP is running. Writing to a FIFO'd register directly while the CP is running can lock up if the CP happens to have filled the FIFO. > > > 2) Can I block radeon interrupt (swi and vbl) and if so how can I do it? > > > What I mean is to block them for a while and not to loose any. Would disabling the interrupts on the chip (by writing to the GEN_INT_CNTL register) be enough for your purpose? Could lose or at least delay interrupts though... -- Earthling Michel Dänzer \ Debian (powerpc), XFree86 and DRI developer Software libre enthusiast \ http://svcs.affero.net/rm.php?r=daenzer ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
