On Fri, 31 May 2002, Tim Smith wrote:
>
> I seem to be observing the behaviour that if, on entry to do_cp_idle() the
> FIFO is not empty already, it never will be empty and the whole thing goes
> pear shaped. Thus, if a big collection of commands is just followed by more
> commands this doesn't seem to cause a problem, but if a big collection of
> commands is followed very quickly by a cp_idle(), it goes funny. This may
> of course be Yet Another Symptom, of which I seem to have chased many :-)
How about trying to change "radeon_do_wait_for_idle()" to _first_ wait for
the RBBM to become unactive, _then_ wait for the fifo to drain, and only
after that do the pixcache flush?
If it is true that the ring buffer commands will fill up the FIFO (which
sounds perfectly sane to me), then that implies that anybody who waits for
the FIFO to empty should first wait for RBBM_ACTIVE to go away.
(That also obviously implies that the ring-buffer-head write must not
be using the FIFO - so you don't need to wait for the fifo to drain in
order to add stuff to the ring buffer - but that does all make sense).
So right now our problem _may_ be that we do this in
radeon_do_wait_for_idle():
- wait for the FIFO to drain
- ring buffer still active, it re-fills the fifo, the engine is still
busy
- now we wait for the ring buffer to go away, and then do the
pixcache_flush(), but since the FIFO has filled up, the actual graphics
engine (as opposed to the ring buffer engine) is still busy, so we
flush the pixcache and in particular we return from
"radeon_do_cp_idle()" while the engine isn't really idle at all.
resulting in either:
- subsequent commands (that assume that the engine is idle) will fail.
- current commands that got into the FIFO may have their rug pulled out
from under them (ie we might have removed some textures that the
commands would need, or something, because the X server thought that
the commands were all done..)
I'm off for a meeting, so I can't test this theory out right now, but it
doesn't sound too crazy to me..
Linus
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