Here's a first stab at the Radeon 3rd texture unit for testing, comments, flames etc.
I'm currently testing this and I'll probably make some of the 0,1,2's
into loops as I do that, but if anyone has a pile of 3 texture demos
they were itching to run... :o)
I've not found much to test it with.
It works in very simple 2 texture tests replacing TEXTURE0 with
TEXTURE2 and mostly with the 'texCombine' test in glean (that's
complaining about results of a few of the tests, mostly DOT3 iirc, but
the single texture tests complain too) it doesn't seem to have broken
any of the existing stuff I run here.
TIA.
--
Michael.
Index: src/tnl_dd/t_dd_vbtmp.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/extras/Mesa/src/tnl_dd/Attic/t_dd_vbtmp.h,v
retrieving revision 1.1.4.2
diff -u -3 -p -r1.1.4.2 t_dd_vbtmp.h
--- src/tnl_dd/t_dd_vbtmp.h 20 Dec 2001 09:51:05 -0000 1.1.4.2
+++ src/tnl_dd/t_dd_vbtmp.h 13 Feb 2002 00:10:20 -0000
@@ -382,6 +384,20 @@ static void TAG(emit)( GLcontext *ctx,
v->v.v1 = tc1[i][1];
}
}
+ if (DO_TEX2) {
+ if (DO_PTEX) {
+ v->pv.u2 = tc2[i][0];
+ v->pv.v1 = tc2[i][1];
+ if (tc2_size == 4)
+ v->pv.q2 = tc2[i][3];
+ else
+ v->pv.q2 = 1.0;
+ }
+ else {
+ v->v.u2 = tc2[i][0];
+ v->v.v2 = tc2[i][1];
+ }
+ }
}
}
}
Index: radeon_context.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v
retrieving revision 1.6.6.4
diff -u -3 -p -r1.6.6.4 radeon_context.c
--- radeon_context.c 6 Nov 2001 16:47:17 -0000 1.6.6.4
+++ radeon_context.c 13 Feb 2002 00:43:06 -0000
@@ -323,7 +323,8 @@ radeonCreateContext( Display *dpy, const
ctx->Const.MaxTextureLevels = 9; /* 256x256 */
}
- ctx->Const.MaxTextureUnits = 2;
+ ctx->Const.MaxTextureLevels = 12; /* 2048x2048 */
+ ctx->Const.MaxTextureUnits = 3;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide points.
@@ -545,6 +546,8 @@ radeonMakeCurrent( __DRIcontextPrivate *
newRadeonCtx->state.hw.dirty |= RADEON_UPLOAD_TEX0;
if ( newRadeonCtx->state.texture.unit[1].texobj )
newRadeonCtx->state.hw.dirty |= RADEON_UPLOAD_TEX1;
+ if ( newRadeonCtx->state.texture.unit[2].texobj )
+ newRadeonCtx->state.hw.dirty |= RADEON_UPLOAD_TEX2;
}
if ( newRadeonCtx->dri.drawable != driDrawPriv ) {
Index: radeon_context.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v
retrieving revision 1.8.6.4
diff -u -3 -p -r1.8.6.4 radeon_context.h
--- radeon_context.h 20 Nov 2001 11:49:21 -0000 1.8.6.4
+++ radeon_context.h 13 Feb 2002 00:43:06 -0000
@@ -224,7 +224,7 @@ struct radeon_dri_mirror {
};
struct radeon_store {
- radeonTexObjPtr texture[2][RADEON_MAX_STATES];
+ radeonTexObjPtr texture[RADEON_MAX_TEXTURE_UNITS][RADEON_MAX_STATES];
drmRadeonState state[RADEON_MAX_STATES];
drmRadeonPrim prim[RADEON_MAX_PRIMS];
GLuint statenr;
Index: radeon_ioctl.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c,v
retrieving revision 1.10.4.11
diff -u -3 -p -r1.10.4.11 radeon_ioctl.c
--- radeon_ioctl.c 11 Dec 2001 11:03:08 -0000 1.10.4.11
+++ radeon_ioctl.c 13 Feb 2002 00:43:06 -0000
@@ -170,6 +170,17 @@ static void emit_state( radeonContextPtr
dest->texture[1].pp_txablend = state->hw.texture[1].pp_txablend;
dest->texture[1].pp_tfactor = state->hw.texture[1].pp_tfactor;
}
+ if ( dirty & RADEON_UPLOAD_TEX2 ) {
+ radeonTexObjPtr t2 = state->texture.unit[2].texobj;
+
+ dest->texture[2].pp_txfilter = t2->pp_txfilter |
+state->hw.texture[2].pp_txfilter;
+ dest->texture[2].pp_txformat = t2->pp_txformat | RADEON_TXFORMAT_ST_ROUTE_STQ2;
+ dest->texture[2].pp_txoffset = t2->pp_txoffset;
+ dest->texture[2].pp_border_color = t2->pp_border_color;
+ dest->texture[2].pp_txcblend = state->hw.texture[2].pp_txcblend;
+ dest->texture[2].pp_txablend = state->hw.texture[2].pp_txablend;
+ dest->texture[2].pp_tfactor = state->hw.texture[2].pp_tfactor;
+ }
}
@@ -220,6 +231,9 @@ static void print_state( drmRadeonState
if ( dirty & RADEON_UPLOAD_TEX1 )
print_values( "TEX1", &state->texture[1], sizeof(state->texture[1]) );
+
+ if ( dirty & RADEON_UPLOAD_TEX2 )
+ print_values( "TEX2", &state->texture[2], sizeof(state->texture[2]) );
}
@@ -250,6 +264,7 @@ static void emit_prim( radeonContextPtr
dirty = RADEON_UPLOAD_CONTEXT_ALL;
if (rmesa->state.texture.unit[0].texobj) dirty |= RADEON_UPLOAD_TEX0;
if (rmesa->state.texture.unit[1].texobj) dirty |= RADEON_UPLOAD_TEX1;
+ if (rmesa->state.texture.unit[2].texobj) dirty |= RADEON_UPLOAD_TEX2;
}
@@ -263,6 +278,7 @@ static void emit_prim( radeonContextPtr
rmesa->store.state[state].dirty = rmesa->state.hw.dirty; /* override */
rmesa->store.texture[0][state] = rmesa->state.texture.unit[0].texobj;
rmesa->store.texture[1][state] = rmesa->state.texture.unit[1].texobj;
+ rmesa->store.texture[2][state] = rmesa->state.texture.unit[2].texobj;
rmesa->state.hw.dirty = 0;
/* print_state( &rmesa->store.state[state] ); */
}
@@ -302,6 +318,8 @@ void radeonFlushPrimsLocked( radeonConte
rmesa->store.state[0].dirty &= ~RADEON_UPLOAD_TEX0;
if ( !rmesa->store.texture[1][0] )
rmesa->store.state[0].dirty &= ~RADEON_UPLOAD_TEX1;
+ if ( !rmesa->store.texture[2][0] )
+ rmesa->store.state[0].dirty &= ~RADEON_UPLOAD_TEX2;
}
@@ -569,6 +587,8 @@ void radeonCopyBuffer( const __DRIdrawab
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX0 );
if ( rmesa->state.texture.unit[1].texobj )
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
+ if ( rmesa->state.texture.unit[2].texobj )
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
rmesa->upload_cliprects = 1;
@@ -787,6 +807,8 @@ static void radeonClear( GLcontext *ctx,
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX0 );
if ( rmesa->state.texture.unit[1].texobj )
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
+ if ( rmesa->state.texture.unit[2].texobj )
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
rmesa->upload_cliprects = 1;
}
Index: radeon_lock.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_lock.c,v
retrieving revision 1.6.4.2
diff -u -3 -p -r1.6.4.2 radeon_lock.c
--- radeon_lock.c 30 Oct 2001 02:19:46 -0000 1.6.4.2
+++ radeon_lock.c 13 Feb 2002 00:43:06 -0000
@@ -88,6 +88,8 @@ void radeonGetLock( radeonContextPtr rme
rmesa->store.state[0].dirty |= RADEON_UPLOAD_TEX0;
if ( rmesa->store.texture[1][0] )
rmesa->store.state[0].dirty |= RADEON_UPLOAD_TEX1;
+ if ( rmesa->store.texture[2][0] )
+ rmesa->store.state[0].dirty |= RADEON_UPLOAD_TEX2;
}
else {
rmesa->state.hw.dirty = RADEON_UPLOAD_CONTEXT_ALL;
@@ -95,6 +97,8 @@ void radeonGetLock( radeonContextPtr rme
rmesa->state.hw.dirty |= RADEON_UPLOAD_TEX0;
if ( rmesa->state.texture.unit[1].texobj )
rmesa->state.hw.dirty |= RADEON_UPLOAD_TEX1;
+ if ( rmesa->state.texture.unit[2].texobj )
+ rmesa->state.hw.dirty |= RADEON_UPLOAD_TEX2;
}
for ( i = 0 ; i < rmesa->texture.numHeaps ; i++ ) {
Index: radeon_render.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/Attic/radeon_render.c,v
retrieving revision 1.1.4.2
diff -u -3 -p -r1.1.4.2 radeon_render.c
--- radeon_render.c 22 Nov 2001 14:00:39 -0000 1.1.4.2
+++ radeon_render.c 13 Feb 2002 00:43:06 -0000
@@ -226,6 +226,9 @@ static void radeon_check_render( GLconte
if (ctx->Texture.Unit[1]._ReallyEnabled)
inputs |= VERT_TEX(1);
+ if (ctx->Texture.Unit[2]._ReallyEnabled)
+ inputs |= VERT_TEX(2);
+
if (ctx->Fog.Enabled)
inputs |= VERT_FOG_COORD;
}
Index: radeon_tex.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c,v
retrieving revision 1.13.2.3
diff -u -3 -p -r1.13.2.3 radeon_tex.c
--- radeon_tex.c 30 Oct 2001 15:12:14 -0000 1.13.2.3
+++ radeon_tex.c 13 Feb 2002 00:43:08 -0000
@@ -323,6 +323,9 @@ static void radeonTexImage1D( GLcontext
if ( t == rmesa->state.texture.unit[1].texobj ) {
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
}
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
+ }
}
@@ -364,6 +367,9 @@ static void radeonTexSubImage1D( GLconte
if ( t == rmesa->state.texture.unit[1].texobj ) {
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
}
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
+ }
}
@@ -403,6 +409,9 @@ static void radeonTexImage2D( GLcontext
if ( t == rmesa->state.texture.unit[1].texobj ) {
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
}
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
+ }
}
@@ -444,6 +453,9 @@ static void radeonTexSubImage2D( GLconte
if ( t == rmesa->state.texture.unit[1].texobj ) {
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
}
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
+ }
}
#if 0
@@ -634,6 +646,9 @@ static void radeonTexParameter( GLcontex
if ( t == rmesa->state.texture.unit[1].texobj ) {
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
}
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
+ }
}
@@ -712,6 +727,18 @@ static void radeonInitTextureObjects( GL
texObj = ctx->Texture.Unit[1].Current2D;
radeonBindTexture( ctx, GL_TEXTURE_2D, texObj );
move_to_tail( &rmesa->texture.swapped,
+ (radeonTexObjPtr)texObj->DriverData );
+
+ ctx->Texture.CurrentUnit = 2;
+
+ texObj = ctx->Texture.Unit[2].Current1D;
+ radeonBindTexture( ctx, GL_TEXTURE_1D, texObj );
+ move_to_tail( &rmesa->texture.swapped,
+ (radeonTexObjPtr)texObj->DriverData );
+
+ texObj = ctx->Texture.Unit[2].Current2D;
+ radeonBindTexture( ctx, GL_TEXTURE_2D, texObj );
+ move_to_tail( &rmesa->texture.swapped,
(radeonTexObjPtr)texObj->DriverData );
ctx->Texture.CurrentUnit = tmp;
Index: radeon_texmem.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c,v
retrieving revision 1.8.4.4
diff -u -3 -p -r1.8.4.4 radeon_texmem.c
--- radeon_texmem.c 7 Nov 2001 00:47:02 -0000 1.8.4.4
+++ radeon_texmem.c 13 Feb 2002 00:43:08 -0000
@@ -82,6 +82,11 @@ void radeonDestroyTexObj( radeonContextP
rmesa->state.texture.unit[1].texobj = NULL;
rmesa->state.hw.dirty &= ~RADEON_UPLOAD_TEX1;
}
+
+ if ( t == rmesa->state.texture.unit[2].texobj ) {
+ rmesa->state.texture.unit[2].texobj = NULL;
+ rmesa->state.hw.dirty &= ~RADEON_UPLOAD_TEX2;
+ }
}
remove_from_list( t );
@@ -517,6 +525,9 @@ int radeonUploadTexImages( radeonContext
if ( t == rmesa->state.texture.unit[1].texobj )
RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX1 );
+
+ if ( t == rmesa->state.texture.unit[2].texobj )
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_TEX2 );
}
/* Let the world know we've used this memory recently */
Index: radeon_texstate.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v
retrieving revision 1.3.6.3
diff -u -3 -p -r1.3.6.3 radeon_texstate.c
--- radeon_texstate.c 30 Oct 2001 15:12:14 -0000 1.3.6.3
+++ radeon_texstate.c 13 Feb 2002 00:43:08 -0000
@@ -142,11 +142,17 @@ static void radeonSetTexImages( radeonCo
*/
firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5);
firstLevel = MAX2(firstLevel, tObj->BaseLevel);
- lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5);
- lastLevel = MAX2(lastLevel, tObj->BaseLevel);
- lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
- lastLevel = MIN2(lastLevel, tObj->MaxLevel);
- lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+ if ( tObj->MinFilter != GL_NEAREST && tObj->MinFilter != GL_LINEAR ) {
+ firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5);
+ firstLevel = MAX2(firstLevel, tObj->BaseLevel);
+ lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5);
+ lastLevel = MAX2(lastLevel, tObj->BaseLevel);
+ lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2);
+ lastLevel = MIN2(lastLevel, tObj->MaxLevel);
+ lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */
+ }
+ else
+ lastLevel = firstLevel;
/* save these values */
t->firstLevel = firstLevel;
@@ -1135,9 +1141,9 @@ static void radeonUpdateTextureUnit( GLc
}
else {
/* Texture unit disabled */
+ RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_CONTEXT );
rmesa->state.texture.unit[unit].texobj = 0;
rmesa->state.hw.dirty &= ~(RADEON_UPLOAD_TEX0 << unit);
- RADEON_STATECHANGE( rmesa, RADEON_UPLOAD_CONTEXT );
rmesa->state.hw.context.pp_cntl &= ~((RADEON_TEX_0_ENABLE |
RADEON_TEX_BLEND_0_ENABLE) << unit);
}
@@ -1149,4 +1155,5 @@ void radeonUpdateTextureState( GLcontext
FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, GL_FALSE );
radeonUpdateTextureUnit( ctx, 0 );
radeonUpdateTextureUnit( ctx, 1 );
+ radeonUpdateTextureUnit( ctx, 2 );
}
Index: radeon_vb.c
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c,v
retrieving revision 1.5.6.6
diff -u -3 -p -r1.5.6.6 radeon_vb.c
--- radeon_vb.c 5 Dec 2001 11:52:33 -0000 1.5.6.6
+++ radeon_vb.c 13 Feb 2002 00:43:09 -0000
@@ -61,8 +61,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RADEON_SPEC_BIT 0x08
#define RADEON_TEX0_BIT 0x10
#define RADEON_TEX1_BIT 0x20
-#define RADEON_PTEX_BIT 0x40
-#define RADEON_MAX_SETUP 0x80
+#define RADEON_TEX2_BIT 0x40
+#define RADEON_PTEX_BIT 0x80
+#define RADEON_MAX_SETUP 0xff
static struct {
void (*emit)( GLcontext *, GLuint, GLuint, void *, GLuint );
@@ -110,7 +111,26 @@ static struct {
RADEON_CP_VC_FRMT_ST1 | \
RADEON_CP_VC_FRMT_Q1)
-#define TEX2_VERTEX_FORMAT 0
+#define TEX2_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
+ RADEON_CP_VC_FRMT_Z | \
+ RADEON_CP_VC_FRMT_W0 | \
+ RADEON_CP_VC_FRMT_PKCOLOR | \
+ RADEON_CP_VC_FRMT_PKSPEC | \
+ RADEON_CP_VC_FRMT_ST0 | \
+ RADEON_CP_VC_FRMT_ST1 | \
+ RADEON_CP_VC_FRMT_ST2)
+
+#define PROJ_TEX2_VERTEX_FORMAT (RADEON_CP_VC_FRMT_XY | \
+ RADEON_CP_VC_FRMT_Z | \
+ RADEON_CP_VC_FRMT_W0 | \
+ RADEON_CP_VC_FRMT_PKCOLOR | \
+ RADEON_CP_VC_FRMT_PKSPEC | \
+ RADEON_CP_VC_FRMT_ST0 | \
+ RADEON_CP_VC_FRMT_Q0 | \
+ RADEON_CP_VC_FRMT_ST1 | \
+ RADEON_CP_VC_FRMT_Q1 | \
+ RADEON_CP_VC_FRMT_ST2 | \
+ RADEON_CP_VC_FRMT_Q2)
#define TEX3_VERTEX_FORMAT 0
#define PROJ_TEX3_VERTEX_FORMAT 0
@@ -120,7 +140,7 @@ static struct {
#define DO_FOG (IND & RADEON_FOG_BIT)
#define DO_TEX0 (IND & RADEON_TEX0_BIT)
#define DO_TEX1 (IND & RADEON_TEX1_BIT)
-#define DO_TEX2 0
+#define DO_TEX2 (IND & RADEON_TEX2_BIT)
#define DO_TEX3 0
#define DO_PTEX (IND & RADEON_PTEX_BIT)
@@ -140,7 +160,7 @@ static struct {
#define HAVE_NOTEX_VERTICES 1
#define HAVE_TEX0_VERTICES 1
#define HAVE_TEX1_VERTICES 1
-#define HAVE_TEX2_VERTICES 0
+#define HAVE_TEX2_VERTICES 1
#define HAVE_TEX3_VERTICES 0
#define HAVE_PTEX_VERTICES 1
@@ -194,6 +214,14 @@ static struct {
#define TAG(x) x##_wgpt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT)
+#define TAG(x) x##_wgt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT|RADEON_PTEX_BIT)
+#define TAG(x) x##_wgpt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|RADEON_TEX0_BIT)
#define TAG(x) x##_wgst0
#include "tnl_dd/t_dd_vbtmp.h"
@@ -213,6 +241,14 @@ static struct {
#define TAG(x) x##_wgspt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT)
+#define TAG(x) x##_wgst0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_SPEC_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT|RADEON_PTEX_BIT)
+#define TAG(x) x##_wgspt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT)
#define TAG(x) x##_wgf
#include "tnl_dd/t_dd_vbtmp.h"
@@ -240,6 +276,14 @@ static struct {
#define TAG(x) x##_wgfpt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT)
+#define TAG(x) x##_wgft0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT|RADEON_PTEX_BIT)
+#define TAG(x) x##_wgfpt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
#define IND (RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT|RADEON_SPEC_BIT|\
RADEON_TEX0_BIT)
#define TAG(x) x##_wgfst0
@@ -260,6 +304,14 @@ static struct {
#define TAG(x) x##_wgfspt0t1
#include "tnl_dd/t_dd_vbtmp.h"
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT|RADEON_SPEC_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT)
+#define TAG(x) x##_wgfst0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
+#define IND
+(RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_FOG_BIT|RADEON_SPEC_BIT|RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT|RADEON_PTEX_BIT)
+#define TAG(x) x##_wgfspt0t1t2
+#include "tnl_dd/t_dd_vbtmp.h"
+
/* Specialized emit, hardwired with q3 strides.
*/
@@ -331,20 +383,28 @@ static void init_setup_tab( void )
init_wgpt0();
init_wgt0t1();
init_wgpt0t1();
+ init_wgt0t1t2();
+ init_wgpt0t1t2();
init_wgst0();
init_wgspt0();
init_wgst0t1();
init_wgspt0t1();
+ init_wgst0t1t2();
+ init_wgspt0t1t2();
init_wgf();
init_wgfs();
init_wgft0();
init_wgfpt0();
init_wgft0t1();
init_wgfpt0t1();
+ init_wgft0t1t2();
+ init_wgfpt0t1t2();
init_wgfst0();
init_wgfspt0();
init_wgfst0t1();
init_wgfspt0t1();
+ init_wgfst0t1t2();
+ init_wgfspt0t1t2();
setup_tab[RADEON_XYZW_BIT|RADEON_RGBA_BIT|RADEON_TEX0_BIT].emit = emit_q3;
}
@@ -353,7 +413,7 @@ static void init_setup_tab( void )
void radeonPrintSetupFlags(char *msg, GLuint flags )
{
- fprintf(stderr, "%s(%x): %s%s%s%s%s%s%s\n",
+ fprintf(stderr, "%s(%x): %s%s%s%s%s%s%s%s\n",
msg,
(int)flags,
(flags & RADEON_XYZW_BIT) ? " xyzw," : "",
@@ -362,6 +422,7 @@ void radeonPrintSetupFlags(char *msg, GL
(flags & RADEON_FOG_BIT) ? " fog," : "",
(flags & RADEON_TEX0_BIT) ? " tex-0," : "",
(flags & RADEON_TEX1_BIT) ? " tex-1," : "",
+ (flags & RADEON_TEX2_BIT) ? " tex-2," : "",
(flags & RADEON_PTEX_BIT) ? " proj-tex," : "");
}
@@ -422,7 +483,9 @@ void radeonChooseVertexState( GLcontext
if (ctx->Fog.Enabled)
ind |= RADEON_FOG_BIT;
- if (ctx->Texture._ReallyEnabled & 0x0f0)
+ if (ctx->Texture._ReallyEnabled & 0xf00)
+ ind |= RADEON_TEX0_BIT|RADEON_TEX1_BIT|RADEON_TEX2_BIT;
+ else if (ctx->Texture._ReallyEnabled & 0x0f0)
ind |= RADEON_TEX0_BIT|RADEON_TEX1_BIT;
else if (ctx->Texture._ReallyEnabled & 0x00f)
ind |= RADEON_TEX0_BIT;
