From: Vandita Kulkarni <[email protected]> Program the computed FRL Link M/N into the transcoder PIPE_LINK_M1/N1 registers along with the other FRL DFM registers, just before enabling the transcoder.
Read it back in the FRL DFM readout for the state checker. v2: Read full 31 bits from LINK_M/N for HDMI FRL. Bspec: 68848 Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Ankit Nautiyal <[email protected]> --- .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c index 8062baed63db..384e92d89e29 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c @@ -725,6 +725,26 @@ bool intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm) return true; } +static void frl_set_m_n(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + intel_de_write(display, PIPE_LINK_M1(display, cpu_transcoder), + crtc_state->frl.link_m); + intel_de_write(display, PIPE_LINK_N1(display, cpu_transcoder), + crtc_state->frl.link_n); +} + +static void frl_get_m_n(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + crtc_state->frl.link_m = intel_de_read(display, PIPE_LINK_M1(display, cpu_transcoder)); + crtc_state->frl.link_n = intel_de_read(display, PIPE_LINK_N1(display, cpu_transcoder)); +} + void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -735,6 +755,8 @@ void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state) if (!crtc_state->frl.enable) return; + frl_set_m_n(crtc_state); + reg = TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans); val = TB_ACTUAL_OFFSET(crtc_state->frl.tb_actual); intel_de_rmw(display, reg, TB_ACTUAL_OFFSET_MASK, val); @@ -753,6 +775,8 @@ void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state) if (!crtc_state->frl.enable) return; + frl_get_m_n(crtc_state); + val = intel_de_read(display, TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans)); crtc_state->frl.tb_actual = REG_FIELD_GET(TB_ACTUAL_OFFSET_MASK, val); -- 2.50.1
