For FRL, port_clock is the link rate, decoupled from the pixel clock, so hsw_crtc_compute_clock() must not overwrite crtc_clock via intel_crtc_dotclock(). The FRL pixel clock isn't recoverable from hardware (the FRL M/N is the DFM tri-byte ratio), so take the sw value in verify_crtc_state() for the derived clock fields.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- .../drm/i915/display/intel_modeset_verify.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 20fd091cb9db..851a4abf2448 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1171,7 +1171,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, return 0; /* CRT dotclock is determined via other means */ - if (!crtc_state->has_pch_encoder) + if (!crtc_state->has_pch_encoder && !crtc_state->frl.enable) crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); return 0; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index f0761d8a7437..54ec1f439b90 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -218,6 +218,24 @@ verify_crtc_state(struct intel_atomic_state *state, if (!sw_crtc_state->hw.active) goto destroy_state; + /* + * The HDMI FRL pixel clock is decoupled from port_clock and cannot be + * recovered from hardware readout. The FRL M/N is the DFM tri-byte ratio, not + * a pixel:link ratio so we cannot derive the pixel clock accurately. + * To avoid mismatches and to avoid handling PIPE_CONF_CHECK for FRL, + * copy the software value to the hardware state. + */ + if (sw_crtc_state->frl.enable) { + hw_crtc_state->hw.adjusted_mode.crtc_clock = + sw_crtc_state->hw.adjusted_mode.crtc_clock; + hw_crtc_state->hw.pipe_mode.crtc_clock = + sw_crtc_state->hw.pipe_mode.crtc_clock; + hw_crtc_state->pixel_rate = + sw_crtc_state->pixel_rate; + hw_crtc_state->pixel_rate_cdclk = + sw_crtc_state->pixel_rate_cdclk; + } + intel_pipe_config_sanity_check(hw_crtc_state); if (!intel_pipe_config_compare(sw_crtc_state, -- 2.50.1
