On Mon, 06 Jul 2026 18:32:40 -0700, Kavan Smith wrote:
> MSM8916 runtime DSI commands still go through
> msm_dsi_host_xfer_prepare(), which re-applies the link clock rate before
> enabling the link clocks. That is fine in principle, but on DSI 6G the
> requested byte clock rate often does not exactly match the DSI PHY PLL's
> realizable rate. For example, the driver can request 56250000 Hz while the
> PLL actually runs at 56246337 Hz.
>
> [...]
Applied to msm-fixes, thanks!
[1/1] drm/msm/dsi: round 6G byte clock rate to the PLL-achievable value
https://gitlab.freedesktop.org/lumag/msm/-/commit/6cd33b6f4155
Best regards,
--
With best wishes
Dmitry
