msm_dsi_host_xfer_prepare() runs for every DSI command, including runtime DCS writes such as backlight (MIPI DCS 0x51), and unconditionally calls link_clk_set_rate() before enabling the link clocks. On MSM8916 (DSI 6G v1.3.1) the requested byte-clock rate never exactly equals the DSI PHY PLL's achievable rate (e.g. 56250000 Hz requested vs 56246337 Hz from the PLL), so the clk framework treats every call as a rate change and re-locks the PLL.
During video-mode operation the byte, pixel and byte-intf clocks are already running and feeding continuous scanout. Re-locking the PLL glitches that live clock. On a video-mode panel with no internal timing generator (e.g. samsung,s6d7aa0 / lsl080al03 on the Samsung Galaxy Tab A 8.0, which regenerates its H/V timing directly from the DSI clock lane) the glitch makes the panel lose pixel lock, producing ~1 second of displaced/wrapped scanout on every DCS command. No FIFO underrun or dsi_err_worker error fires; it is a silent clock-domain glitch. Stock (downstream MDSS) firmware sends the same 0x51 with CMD_CLK_CTRL, which only refcount-enables the clocks and never re-runs clk_set_rate, and does not glitch. The link rate is already programmed at power-on by msm_dsi_host_power_on(), so skip the redundant re-set once the link is up; init-time transfers (before power_on) still set the rate. Link: https://lists.freedesktop.org/archives/dri-devel/2018-April/172218.html Signed-off-by: Kavan Smith <[email protected]> --- drivers/gpu/drm/msm/dsi/dsi_host.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2170,7 +2170,17 @@ * mdp clock need to be enabled to receive dsi interrupt */ pm_runtime_get_sync(&msm_host->pdev->dev); - cfg_hnd->ops->link_clk_set_rate(msm_host); + /* + * Don't re-set the link clock rate when the link is already up. The + * requested byte-clock rate rarely equals the DSI PHY PLL's achievable + * rate, so clk_set_rate() re-locks the PLL on every command; for a + * video-mode panel with no internal timing generator that clock glitch + * makes the panel lose pixel lock mid-scanout (~1s of displaced image on + * each DCS write, e.g. every backlight update). The rate is already set + * at power-on. + */ + if (!msm_host->power_on) + cfg_hnd->ops->link_clk_set_rate(msm_host); cfg_hnd->ops->link_clk_enable(msm_host); /* TODO: vote for bus bandwidth */
