On 7/5/26 9:13 PM, Anna Maniscalco wrote: > Previously both SID 0 and 1 where associated with the same domain. > > When LPAC is not used this is needed so firmware can acces memory when > initializing using the same page table as GFX. > > To use LPAC however we need to move SID 1 to a different device. > > Signed-off-by: Anna Maniscalco <[email protected]> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi > b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 1604bc8cff37..44e5f9d4b335 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -4133,6 +4133,13 @@ tcsr: clock-controller@1fc0000 { > #reset-cells = <1>; > }; > > + lpac: lpac@3d00000 { > + compatible = "qcom,lpac"; > + reg = <0x0 0x03d00000 0x0 0x61000>; > + > + iommus = <&adreno_smmu 1 0x0>; > + };
I think this could work better as a subnode of the GPU (or perhaps if there's no "actual" separate address space, maybe just iommu-maps? for something also making use of the latter, see patches 1-5 of: https://lore.kernel.org/all/[email protected]/ Konrad
