We want the context bank used by LPAC to use split address space just like GFX.
Signed-off-by: Anna Maniscalco <[email protected]> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index edd41b5a3b6a..48a590aaeb5e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -35,6 +35,8 @@ static const struct of_device_id qcom_smmu_actlr_client_of_match[] = { { .compatible = "qcom,adreno", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible = "qcom,lpac", + .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,adreno-gmu", .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, { .compatible = "qcom,adreno-smmu", @@ -217,6 +219,7 @@ static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_a } #define QCOM_ADRENO_SMMU_GPU_SID 0 +#define QCOM_ADRENO_SMMU_LPAC_SID 1 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) { @@ -230,7 +233,8 @@ static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) for (i = 0; i < fwspec->num_ids; i++) { u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); - if (sid == QCOM_ADRENO_SMMU_GPU_SID) + if (sid == QCOM_ADRENO_SMMU_GPU_SID || + sid == QCOM_ADRENO_SMMU_LPAC_SID) return true; } @@ -305,9 +309,9 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma */ if (qcom_adreno_smmu_is_gpu_device(dev)) { start = 0; - count = 1; + count = 2; } else { - start = 1; + start = 2; count = smmu->num_context_banks; } @@ -394,6 +398,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, + { .compatible = "qcom,lpac" }, { .compatible = "qcom,adreno-gmu" }, { .compatible = "qcom,glymur-mdss" }, { .compatible = "qcom,mdp4" }, -- 2.54.0
