在 2026-06-25四的 17:44 +0800，Joey Lu写道： > The Nuvoton MA35D1 SoC integrates a DCUltraLite display controller > whose > AXI and AHB bus clocks share a single gate enable bit with the > display > core clock, so the clock driver does not expose them separately. This > patch makes the axi and ahb clocks optional in the probe. > > Signed-off-by: Joey Lu <[email protected]>
``` Reviewed-by: Icenowy Zheng <[email protected]> ``` Thanks, Icenowy > --- > drivers/gpu/drm/verisilicon/vs_dc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c > b/drivers/gpu/drm/verisilicon/vs_dc.c > index 9729b693d360..fd1f5fe67a68 100644 > --- a/drivers/gpu/drm/verisilicon/vs_dc.c > +++ b/drivers/gpu/drm/verisilicon/vs_dc.c > @@ -90,13 +90,13 @@ static int vs_dc_probe(struct platform_device > *pdev) > return PTR_ERR(dc->core_clk); > } > > - dc->axi_clk = devm_clk_get_enabled(dev, "axi"); > + dc->axi_clk = devm_clk_get_optional_enabled(dev, "axi"); > if (IS_ERR(dc->axi_clk)) { > dev_err(dev, "can't get axi clock\n"); > return PTR_ERR(dc->axi_clk); > } > > - dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); > + dc->ahb_clk = devm_clk_get_optional_enabled(dev, "ahb"); > if (IS_ERR(dc->ahb_clk)) { > dev_err(dev, "can't get ahb clock\n"); > return PTR_ERR(dc->ahb_clk);
