The Nuvoton MA35D1 SoC integrates a Verisilicon DCUltraLite display controller (DC8000 generation) whose register layout differs from the DC8200 in several important ways:
1. No CONFIG_EX commit path: framebuffer updates use the enable (bit 0) and reset (bit 4) bits in FB_CONFIG instead of the DC8200 staging registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, PANEL_CONFIG_EX). 2. No PANEL_START register: panel output starts when PANEL_CONFIG.RUNNING is set; there is no multi-display sync start register. 3. Different IRQ registers: DCUltraLite uses DISP_IRQ_STA (0x147C) / DISP_IRQ_EN (0x1480) versus DC8200's TOP_IRQ_ACK (0x0010) / TOP_IRQ_EN (0x0014). 4. Simpler clock topology: only 'core' (bus gate) and 'pix0' (pixel divider) clocks; no axi or ahb clocks required. Signed-off-by: Joey Lu <[email protected]> --- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_dc.c | 5 +- drivers/gpu/drm/verisilicon/vs_dc.h | 1 + drivers/gpu/drm/verisilicon/vs_dc8000.c | 86 +++++++++++++++++++++++++ 4 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8000.c diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile index 9d4cd16452fa..d2fd8e4dff24 100644 --- a/drivers/gpu/drm/verisilicon/Makefile +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_drm.o vs_hwdb.o \ +verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_dc8200.o vs_dc8000.o vs_drm.o vs_hwdb.o \ vs_plane.o vs_primary_plane.o vs_cursor_plane.o obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index fd1f5fe67a68..9499fffbca58 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -134,7 +134,10 @@ static int vs_dc_probe(struct platform_device *pdev) dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, dc->identity.revision, dc->identity.customer_id); - dc->funcs = &vs_dc8200_funcs; + if (dc->identity.generation == VSDC_GEN_DC8200) + dc->funcs = &vs_dc8200_funcs; + else + dc->funcs = &vs_dc8000_funcs; if (port_count > dc->identity.display_count) { dev_err(dev, "too many downstream ports than HW capability\n"); diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h index 825f5dd6bf17..ac96ad701199 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.h +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -66,5 +66,6 @@ struct vs_dc { }; extern const struct vs_dc_funcs vs_dc8200_funcs; +extern const struct vs_dc_funcs vs_dc8000_funcs; #endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc8000.c b/drivers/gpu/drm/verisilicon/vs_dc8000.c new file mode 100644 index 000000000000..fbe0fa516cac --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc8000.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Joey Lu <[email protected]> + */ + +#include <linux/regmap.h> + +#include "vs_crtc_regs.h" +#include "vs_dc.h" +#include "vs_drm.h" +#include "vs_primary_plane_regs.h" + +static void vs_dc8000_panel_enable_ex(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dc8000_panel_disable_ex(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_RESET); +} + +static void vs_dc8000_crtc_begin(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dc8000_crtc_flush(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_VALID); +} + +static void vs_dc8000_crtc_enable_ex(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dc8000_crtc_disable_ex(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_ENABLE); +} + +static void vs_dc8000_enable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_set_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static void vs_dc8000_disable_vblank(struct vs_dc *dc, unsigned int output) +{ + regmap_clear_bits(dc->regs, VSDC_DISP_IRQ_EN, + VSDC_DISP_IRQ_VSYNC(output)); +} + +static u32 vs_dc8000_irq_ack(struct vs_dc *dc) +{ + u32 hw_irqs, unified = 0; + unsigned int i; + + regmap_read(dc->regs, VSDC_DISP_IRQ_STA, &hw_irqs); + + for (i = 0; i < VSDC_MAX_OUTPUTS; i++) { + if (hw_irqs & VSDC_DISP_IRQ_VSYNC(i)) + unified |= VSDC_IRQ_VSYNC(i); + } + + return unified; +} + +const struct vs_dc_funcs vs_dc8000_funcs = { + .panel_enable_ex = vs_dc8000_panel_enable_ex, + .panel_disable_ex = vs_dc8000_panel_disable_ex, + .crtc_begin = vs_dc8000_crtc_begin, + .crtc_flush = vs_dc8000_crtc_flush, + .crtc_enable_ex = vs_dc8000_crtc_enable_ex, + .crtc_disable_ex = vs_dc8000_crtc_disable_ex, + .enable_vblank = vs_dc8000_enable_vblank, + .disable_vblank = vs_dc8000_disable_vblank, + .irq_ack = vs_dc8000_irq_ack, +}; -- 2.43.0
