Add vspd0 node to RZ/G3E SoC DTSI.

Signed-off-by: Tommaso Merciai <[email protected]>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi 
b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 9db3428fe810..876d8e3903a2 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1193,6 +1193,20 @@ fcpvd0: fcp@16470000 {
                        resets = <&cpg 0xdc>;
                        power-domains = <&cpg>;
                };
+
+               vspd0: vsp@16480000 {
+                       compatible = "renesas,r9a09g047-vsp2",
+                                    "renesas,r9a07g044-vsp2";
+                       reg = <0 0x16480000 0 0x10000>;
+                       interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xed>,
+                                <&cpg CPG_MOD 0xee>,
+                                <&cpg CPG_MOD 0xef>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       resets = <&cpg 0xdc>;
+                       power-domains = <&cpg>;
+                       renesas,fcp = <&fcpvd0>;
+               };
        };
 
        stmmac_axi_setup: stmmac-axi-config {
-- 
2.43.0

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