Hi Hugo,
On Thu, 20 Nov 2025 at 15:47, Hugo Villeneuve <[email protected]> wrote:
> On Tue, 18 Nov 2025 21:27:43 -0500
> Chris Brandt <[email protected]> wrote:
> > Convert the limited MIPI clock calculations to a full range of settings
> > based on math including H/W limitation validation.
> > Since the required DSI division setting must be specified from external
> > sources before calculations, expose a new API to set it.
> >
> > Signed-off-by: Chris Brandt <[email protected]>
> > Reviewed-by: Biju Das <[email protected]>
> > Tested-by: Biju Das <[email protected]>
> > --- a/include/linux/clk/renesas.h
> > +++ b/include/linux/clk/renesas.h
> > @@ -16,6 +16,11 @@ struct device;
> > struct device_node;
> > struct generic_pm_domain;
> >
> > +enum {
> > + PLL5_TARGET_DPI,
> > + PLL5_TARGET_DSI
> > +};
> > +
> > void cpg_mstp_add_clk_domain(struct device_node *np);
> > #ifdef CONFIG_CLK_RENESAS_CPG_MSTP
> > int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device
> > *dev);
> > @@ -32,4 +37,11 @@ void cpg_mssr_detach_dev(struct generic_pm_domain
> > *unused, struct device *dev);
> > #define cpg_mssr_attach_dev NULL
> > #define cpg_mssr_detach_dev NULL
> > #endif
> > +
> > +#ifdef CONFIG_CLK_RZG2L
> > +void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target);
> > +#else
> > +static inline void rzg2l_cpg_dsi_div_set_divider(u8, int target) { }
>
> Maybe use:
>
> #define rzg2l_cpg_dsi_div_set_divider(...) do { } while (0)
I assume you are saying this in the context of the kernel test robot's
report?
Static inline functions offer more safety. Just s/u8/u8 divider/ should
fix the W=1 issue.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
