+ if (nvdev->resmem.memlength && region_index == RESMEM_REGION_INDEX) {
+ /*
+ * The P2P properties of the non-BAR memory is the same as the
+ * BAR memory, so just use the provider for index 0. Someday
+ * when CXL gets P2P support we could create CXLish providers
+ * for the non-BAR memory.
+ */
+ mem_region = &nvdev->resmem;
+ } else if (region_index == USEMEM_REGION_INDEX) {
+ /*
+ * This is actually cachable memory and isn't treated as P2P in
+ * the chip. For now we have no way to push cachable memory
+ * through everything and the Grace HW doesn't care what caching
+ * attribute is programmed into the SMMU. So use BAR 0.
+ */
+ mem_region = &nvdev->usemem;
+ }
+
Can we replace this with nvgrace_gpu_memregion()?
