> From: Leon Romanovsky <[email protected]> > Sent: Tuesday, November 11, 2025 5:58 PM > > From: Jason Gunthorpe <[email protected]> > > Call vfio_pci_core_fill_phys_vec() with the proper physical ranges for the > synthetic BAR 2 and BAR 4 regions. Otherwise use the normal flow based on > the PCI bar. > > This demonstrates a DMABUF that follows the region info report to only > allow mapping parts of the region that are mmapable. Since the BAR is > power of two sized and the "CXL" region is just page aligned the there can > be a padding region at the end that is not mmaped or passed into the > DMABUF. > > The "CXL" ranges that are remapped into BAR 2 and BAR 4 areas are not PCI > MMIO, they actually run over the CXL-like coherent interconnect and for > the purposes of DMA behave identically to DRAM. We don't try to model this > distinction between true PCI BAR memory that takes a real PCI path and the > "CXL" memory that takes a different path in the p2p framework for now. > > Signed-off-by: Jason Gunthorpe <[email protected]> > Tested-by: Alex Mastro <[email protected]> > Tested-by: Nicolin Chen <[email protected]> > Signed-off-by: Leon Romanovsky <[email protected]>
Reviewed-by: Kevin Tian <[email protected]>
