[AMD Official Use Only - AMD Internal Distribution Only] Hi Sean,
Thank you for the patch. > -----Original Message----- > From: Sean Anderson <[email protected]> > Sent: Thursday, November 13, 2025 12:37 PM > To: Laurent Pinchart <[email protected]>; Tomi Valkeinen > <[email protected]>; [email protected] > Cc: [email protected]; Mike Looijmans <[email protected]>; > David Airlie <[email protected]>; Thomas Zimmermann > <[email protected]>; Maarten Lankhorst > <[email protected]>; Klymenko, Anatoliy > <[email protected]>; Maxime Ripard <[email protected]>; linux- > [email protected]; Simona Vetter <[email protected]>; Simek, > Michal <[email protected]>; Sean Anderson > <[email protected]> > Subject: [PATCH 3/3] drm: zynqmp: Add blend mode property to graphics plane > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > When global alpha is enabled, per-pixel alpha is ignored. Allow > userspace to explicitly specify whether to use per-pixel alpha by > exposing it through the blend mode property. I'm not sure whether the > per-pixel alpha is pre-multiplied or not [1], but apparently it *must* be > pre-multiplied so I guess we have to advertise it. > > [1] All we get is "The alpha value available with the graphics stream > will define the transparency of the graphics." > > Signed-off-by: Sean Anderson <[email protected]> > --- > > drivers/gpu/drm/xlnx/zynqmp_kms.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c > b/drivers/gpu/drm/xlnx/zynqmp_kms.c > index 456ada9ac003..fa1cfc16db36 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c > @@ -61,6 +61,13 @@ static int zynqmp_dpsub_plane_atomic_check(struct > drm_plane *plane, > if (!new_plane_state->crtc) > return 0; > > + if (new_plane_state->pixel_blend_mode != > DRM_MODE_BLEND_PIXEL_NONE && > + new_plane_state->alpha >> 8 != 0xff) { > + drm_dbg_kms(plane->dev, > + "Plane alpha must be 1.0 when using pixel > alpha\n"); > + return -EINVAL; > + } > + > crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); > if (IS_ERR(crtc_state)) > return PTR_ERR(crtc_state); > @@ -117,9 +124,13 @@ static void > zynqmp_dpsub_plane_atomic_update(struct drm_plane *plane, > > zynqmp_disp_layer_update(layer, new_state); > > - if (plane->index == ZYNQMP_DPSUB_LAYER_GFX) > - zynqmp_disp_blend_set_global_alpha(dpsub->disp, true, > + if (plane->index == ZYNQMP_DPSUB_LAYER_GFX) { > + bool blend = plane->state->pixel_blend_mode == > + DRM_MODE_BLEND_PIXEL_NONE; > + > + zynqmp_disp_blend_set_global_alpha(dpsub->disp, blend, > plane->state->alpha >> 8); > + } > > /* > * Unconditionally enable the layer, as it may have been disabled > @@ -179,9 +190,18 @@ static int zynqmp_dpsub_create_planes(struct > zynqmp_dpsub *dpsub) > return ret; > > if (i == ZYNQMP_DPSUB_LAYER_GFX) { > + unsigned int blend_modes = > + BIT(DRM_MODE_BLEND_PIXEL_NONE) | > + BIT(DRM_MODE_BLEND_PREMULTI); | BIT(DRM_MODE_BLEND_COVERAGE) - this is what implemented in the hardware. > + > ret = drm_plane_create_alpha_property(plane); > if (ret) > return ret; > + > + ret = drm_plane_create_blend_mode_property(plane, > + > blend_modes); > + if (ret) > + return ret; > } > } > > -- > 2.35.1.1320.gc452695387.dirty Thank you, Anatoliy
