> Subject: [PATCH v3 04/10] drm/i915/alpm: Refactor Auxless wake time > calculation > > Divide the auxless wake time calculation in parts which will help later to add > Xe3p related modification. > > v2: Refactor first existing calculation. [Jani] > v3: Cosmetic changes. [Jani, Suraj] > > Bspec: 71477 > Cc: Jouni Högander <[email protected]> > Signed-off-by: Animesh Manna <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++++------- > 1 file changed, 22 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c > b/drivers/gpu/drm/i915/display/intel_alpm.c > index 3e271de5504b..b4b874dd3725 100644 > --- a/drivers/gpu/drm/i915/display/intel_alpm.c > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c > @@ -98,6 +98,25 @@ static int get_lfps_half_cycle_clocks(const struct > intel_crtc_state *crtc_state) > 1000 / (2 * LFPS_CYCLE_COUNT); > } > > +static int get_tphy2_p2_to_p0(const struct intel_crtc_state > +*crtc_state) { > + return 12 * 1000; > +} > + > +static int get_establishment_period(const struct intel_crtc_state > +*crtc_state) { > + int t1 = 50 * 1000; > + int tps4 = 252; > + /* port_clock is link rate in 10kbit/s units */ > + int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock; > + int tcds, establishment_period; > + > + tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock; > + establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds); > + > + return establishment_period; > +} > + > /* > * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ > * tSilence, Max+ tPHY Establishment + tCDS) / tline) @@ -119,17 +138,11 > @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state > *crtc_state) > */ > static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state > *crtc_state) { > - int tphy2_p2_to_p0 = 12 * 1000; > - int t1 = 50 * 1000; > - int tps4 = 252; > - /* port_clock is link rate in 10kbit/s units */ > - int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock; > - int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; > - int t2 = num_ml_phy_lock * tml_phy_lock; > - int tcds = 1 * t2; > + int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state); > + int establishment_period = get_establishment_period(crtc_state); > > return DIV_ROUND_UP(tphy2_p2_to_p0 + > get_lfps_cycle_time(crtc_state) + > - SILENCE_PERIOD_TIME + t1 + tcds, 1000); > + establishment_period, 1000); > } > > static int > -- > 2.29.0
