On Mon, Oct 27, 2025 at 03:21:33PM +0200, Dmitry Baryshkov wrote: > On Fri, Oct 24, 2025 at 10:59:07AM +0800, yuanjiey wrote: > > On Thu, Oct 23, 2025 at 02:59:12PM +0300, Dmitry Baryshkov wrote: > > > On Thu, Oct 23, 2025 at 03:53:52PM +0800, yuanjie yang wrote: > > > > From: Yuanjie Yang <[email protected]> > > > > > > > > DPU version 13 introduces changes to the interrupt register > > > > layout. Update the driver to support these modifications for > > > > proper interrupt handling. > > > > > > So... Previous patch enabled support for the platform and it has been > > > using wrong registers for interrupts? I think that's broken. > > > > I want to express DPU 13 has different INTF register address, so need to > > add new > > interrupt array to let DPU 13 interrupt work fine. Maybe I should optimize > > my commit msg. > > Make sure that patches are structured logically. You can not enable > support for the hardware if the interrupts are not (yet) handled.
Kaanapali Dpu interrupts: INTR_IDX_VSYNC, INTR_IDX_PINGPONG, INTR_IDX_UNDERRUN, INTR_IDX_CTL_START, INTR_IDX_RDPTR, INTR_IDX_WB_DONE, are handled by irq handler, so here enable dpu_intr_set_13xx. Thanks, Yuanjie > > -- > With best wishes > Dmitry
