Hi Chris, > -----Original Message----- > From: Chris Brandt <[email protected]> > Sent: 28 October 2025 19:43 > Subject: RE: [PATCH v3 1/2] clk: renesas: rzg2l: Remove DSI clock rate > restrictions > > Hi Biju, > > On Tue, Oct 28, 2025 3:07 PM, Biju Das wrote: > > > > However, current defaults today in the driver are illegal for DPI, > > > even though they clearly work in real life on all the RZ/G2UL boards. > > > priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */ > > > priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */ > > > priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */ > > > > > > Side note, that code comment "Use clk src 1 for DSI " is wrong ...it > > > should say "DPI" > > > > Why? > > > > This is correct as per hardware manual page 283 and [1] and [2] > > For "DPI", both RZ/G2L and RZ/G2UL have the same table and same restrictions. > > Valid values for register bits for DIVDSIA_SET = 1,2,3 Valid values for > register bits for DIVDSIB_SET > = 0 > > Remember, this is for DPI (not MIPI-DSI) > > You were the one that pointed this out to me. > > The driver needs to default to DPI mode (PLL5_TARGET_DPI ) because for > RZ/G2UL, no one is going to > call the new API to change it. > > > > priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */ > > > priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */ > > So the current defaults of DIV_B = 2 is no good. > DIV_B must always be '0' > > > I just changed the code to this, > > /* Default settings for DPI */ > priv->mux_dsi_div_params.clksrc = 1; > priv->mux_dsi_div_params.dsi_div_a = 3; /* Divided by 8 */ > priv->mux_dsi_div_params.dsi_div_b = 0; /* Divided by 1 */ > dsi_div_ab = (priv->mux_dsi_div_params.dsi_div_b + 1) << > priv->mux_dsi_div_params.dsi_div_a; > > And on a RZ/G2UL (DPI) EVK, resolutions between 640x48 to 1920x1080 all work. > > Do you agree? Or am I missing something?
I was referring to your comment " Side note, that code comment "Use clk src 1 for DSI " is wrong ...it should say "DPI"" DPI always use FOUTPOSTDIV. So, clksrc=0 always for RZ/G2UL. See [1] and [2] It is illegal clksrc=1(FOUT1PH0) for RZ/G2UL. You can cross check mux register value with RZ/G2UL. DSI uses mux and it can take clksrc=0(FOUTPOSTDIV) or clksrc=1(FOUT1PH0) [1] https://elixir.bootlin.com/linux/v6.18-rc3/source/drivers/clk/renesas/r9a07g043-cpg.c#L159 [2] https://elixir.bootlin.com/linux/v6.18-rc3/source/drivers/clk/renesas/rzg2l-cpg.c#L738 Cheers, Biju
