Hi Chris, > -----Original Message----- > From: Chris Brandt <[email protected]> > Sent: 28 October 2025 17:46 > Subject: RE: [PATCH v3 1/2] clk: renesas: rzg2l: Remove DSI clock rate > restrictions > > Hi Hugo, > > On Tue, Oct 28, 2025 12:39 PM, Hugo Villeneuve wrote: > > > > > If we arrive at this point, it seems that these values: > > > > priv->mux_dsi_div_params.dsi_div_a > > > > priv->mux_dsi_div_params.dsi_div_b > > > > > > > > were not initialised by the previous loop. Is this expected? If yes, > > > > maybe a comment would help? > > > > So are the uninitialised values valid at all? > > Actually, after some more testing......I remember what I did. > > The PLL5 needs to support both the MIPI-DSI and DPI (Parallel) use cases. > > But, since the execution paths are different in the kernel for MIPI vs DPI, I > needed to make the > default settings for DPI knowing that if MIPI-DSI was used, they would get > overwritten (hence the new > API was introduced) > > However, current defaults today in the driver are illegal for DPI, even > though they clearly work in > real life on all the RZ/G2UL boards. > priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */ > priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */ > priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */ > > Side note, that code comment "Use clk src 1 for DSI " is wrong ...it should > say "DPI"
Why? This is correct as per hardware manual page 283 and [1] and [2] [1] https://elixir.bootlin.com/linux/v6.18-rc3/source/drivers/clk/renesas/r9a07g044-cpg.c#L142 -->RZ/G2L. [2] https://elixir.bootlin.com/linux/v6.18-rc3/source/drivers/clk/renesas/r9a07g043-cpg.c#L159 -->RZ/G2UL Cheers, Biju
