On 10/15/2025, Rob Herring wrote:
> On Sat, Oct 11, 2025 at 06:51:16PM +0200, Marek Vasut wrote:
>> i.MX95 Display Controller display engine consists of all processing
>> units that operate in a display clock domain. Document DomainBlend
>> block which is specific to i.MX95 and required to get any display
>> output on that SoC.
>>
>> Signed-off-by: Marek Vasut <[email protected]>
>> ---
>> Cc: Abel Vesa <[email protected]>
>> Cc: Conor Dooley <[email protected]>
>> Cc: Fabio Estevam <[email protected]>
>> Cc: Krzysztof Kozlowski <[email protected]>
>> Cc: Laurent Pinchart <[email protected]>
>> Cc: Liu Ying <[email protected]>
>> Cc: Lucas Stach <[email protected]>
>> Cc: Peng Fan <[email protected]>
>> Cc: Pengutronix Kernel Team <[email protected]>
>> Cc: Rob Herring <[email protected]>
>> Cc: Shawn Guo <[email protected]>
>> Cc: Thomas Zimmermann <[email protected]>
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> ---
>> .../display/imx/fsl,imx95-dc-domainblend.yaml | 32 +++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/imx/fsl,imx95-dc-domainblend.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/imx/fsl,imx95-dc-domainblend.yaml
>>
>> b/Documentation/devicetree/bindings/display/imx/fsl,imx95-dc-domainblend.yaml
>> new file mode 100644
>> index 0000000000000..703f98e3321e8
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/display/imx/fsl,imx95-dc-domainblend.yaml
>> @@ -0,0 +1,32 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>> http://devicetree.org/schemas/display/imx/fsl,imx95-dc-domainblend.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Freescale i.MX95 Display Controller Domain Blend Unit
>> +
>> +description: Combines two input frames to a single output frame.
I'd like to comment on patches in split patch serieses(to be sent if needed).
But, since I provide the below interrupt information, anyway I take the chance
to comment more:
Add more description about the unit according to i.MX95 DC IP spec:
The unit operates in four modes:
- Primary mode: The primary input is used for output.
- Secondary mode: The secondary input is used for output.
- Blend mode: Primary and secondary inputs are blended, according to the
programmed blending functions.
- SidebySide mode: Primary and secondary streams are projected side by side,
i.e., primary video on the left side and secondary on the
right.
BTW, I confirm that two Domain Blend Units exist in i.MX95 DC while they don't
exist in i.MX8qxp/qm DCs. And, as you can see, this unit supports multiple
modes, this would impact how an OS implements a display driver a lot, especially
Blend mode and SidebySide mode.
>> +
>> +maintainers:
>> + - Marek Vasut <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + const: fsl,imx95-dc-domainblend
>> +
>> + reg:
>> + maxItems: 1
>
> No clocks or other resources?
As patch 39 shows, there are 3 interrupts - domainblend{0,1}_shdload,
domainblend{0,1}_framecomplete and domainblend{0,1}_seqcomplete.
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + domainblend@4b6a0000 {
>> + compatible = "fsl,imx95-dc-domainblend";
>> + reg = <0x4b6a0000 0x10>;
>> + };
>> --
>> 2.51.0
>>
--
Regards,
Liu Ying
