From: Joel Fernandes <[email protected]> This will be needed by both the GSP boot code as well as GSP resume code in the sequencer.
Signed-off-by: Joel Fernandes <[email protected]> Reviewed-by: Lyude Paul <[email protected]> --- Changes for v5: - Make it infallible --- drivers/gpu/nova-core/falcon.rs | 8 ++++++++ drivers/gpu/nova-core/regs.rs | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 185ed6d1cfb8..c871fd061987 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -515,4 +515,12 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool { let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); cpuctl.active_stat() } + + /// Write the application version to the OS register. + #[expect(dead_code)] + pub(crate) fn write_os_version(&self, bar: &Bar0, app_version: u32) { + regs::NV_PFALCON_FALCON_OS::default() + .set_value(app_version) + .write(bar, &E::ID); + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 3bd1bddb16bb..6eda5c44c599 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -215,6 +215,12 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> { 31:0 value as u32; }); +// Used to store version information about the firmware running +// on the Falcon processor. +register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] { + 31:0 value as u32; +}); + register!(NV_PFALCON_FALCON_RM @ PFalconBase[0x00000084] { 31:0 value as u32; }); -- 2.50.1
