On 10/6/25 3:39 AM, Ayushi Makhija wrote:
> The QCS8300 SoC uses the 5nm (v4.2) DSI PHY driver.
>
> Signed-off-by: Ayushi Makhija <[email protected]>
> ---
[...]
> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8300_cfgs = {
> + .has_phy_lane = true,
> + .regulator_data = dsi_phy_7nm_48000uA_regulators,
> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_48000uA_regulators),
> + .ops = {
> + .enable = dsi_7nm_phy_enable,
> + .disable = dsi_7nm_phy_disable,
> + .pll_init = dsi_pll_7nm_init,
> + .save_pll_state = dsi_7nm_pll_save_state,
> + .restore_pll_state = dsi_7nm_pll_restore_state,
> + .set_continuous_clock = dsi_7nm_set_continuous_clock,
> + },
> + .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> + .io_start = { 0xae94400 },
> + .num_dsi_phy = 1,
> + .quirks = DSI_PHY_7NM_QUIRK_V4_2,
> +};
Again, this is not necessary, since the lookup code looks like this:
for (i = 0; i < cfg->num_dsi_phy; i++) {
if (cfg->io_start[i] == res->start)
return i;
}
Konrad
