On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
>> Add device tree nodes for the DSI0 controller with their corresponding
>> PHY found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Ayushi Makhija <quic_amakh...@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
>> 1 file changed, 94 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index e0e1f63fc45b..834ae0522f2f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>> @@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
>> remote-endpoint =
>> <&mdss_dp0_in>;
>> };
>> };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint =
>> <&mdss_dsi0_in>;
>> + };
>> + };
>> };
>>
>> mdp_opp_table: opp-table {
>> @@ -4881,6 +4889,89 @@ opp-650000000 {
>> };
>> };
>>
>> + mdss_dsi0: dsi@ae94000 {
>> + compatible =
>> "qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
>
> qcom,qcs8300-dsi-ctrl. You might use three compatibles (qcs8300, sa8775p
> and the generic one), but there should be qcs8300 one.
>
> Also please add a whitespace after comma or (even better), keep one
> compat per line (align on opening quote).
>
>> + reg = <0x0 0x0ae94000 0x0 0x400>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <4>;
>> +
>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
>> + <&dispcc
>> MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>;
>> + clock-names = "byte",
>> + "byte_intf",
>> + "pixel",
>> + "core",
>> + "iface",
>> + "bus";
>> +
>> + assigned-clocks = <&dispcc
>> MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> + <&dispcc
>> MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> + assigned-clock-parents = <&mdss_dsi0_phy
>> DSI_BYTE_PLL_CLK>,
>> + <&mdss_dsi0_phy
>> DSI_PIXEL_PLL_CLK>;
>> +
>> + phys = <&mdss_dsi0_phy>;
>> +
>> + operating-points-v2 = <&mdss_dsi_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + mdss_dsi0_in: endpoint {
>> + remote-endpoint =
>> <&dpu_intf1_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + mdss_dsi0_out: endpoint {
>> + };
>> + };
>> + };
>> +
>> + mdss_dsi_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-358000000 {
>> + opp-hz = /bits/ 64 <358000000>;
>> + required-opps =
>> <&rpmhpd_opp_svs_l1>;
>> + };
>> + };
>> + };
>> +
>> + mdss_dsi0_phy: phy@ae94400 {
>> + compatible = "qcom,sa8775p-dsi-phy-5nm";
>
> Add qcs8300-specific compatible and use sa8775p as a fallback
>
Hi Dmitry,
I have one doubt, even though the ctrl and phy versions for sa8775p(LeMans) and
qcs8300(Monaco) are same.
Why can't we use the same compatible string that we have used for LeMans ctrl
and phy ? what is the need to define a separate
compatible string for monaco ctrl and phy ?
Thanks,
Ayushi
