Add device tree nodes for the DSI0 controller with their corresponding PHY found on Qualcomm QCS8300 SoC.
Signed-off-by: Ayushi Makhija <quic_amakh...@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 95 ++++++++++++++++++++++++++-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index e0e1f63fc45b..834ae0522f2f 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
@@ -4854,6 +4855,13 @@ dpu_intf0_out: endpoint {
remote-endpoint =
<&mdss_dp0_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<&mdss_dsi0_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -4881,6 +4889,89 @@ opp-650000000 {
};
};
+ mdss_dsi0: dsi@ae94000 {
+ compatible =
"qcom,sa8775p-dsi-ctrl","qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x0ae94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc
MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc
MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc
MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy
DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy
DSI_PIXEL_PLL_CLK>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint =
<&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sa8775p-dsi-phy-5nm";
+ reg = <0x0 0x0ae94400 0x0 0x200>,
+ <0x0 0x0ae94600 0x0 0x280>,
+ <0x0 0x0ae94900 0x0 0x27c>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy",
"qcom,sa8775p-edp-phy";
@@ -5008,7 +5099,9 @@ dispcc: clock-controller@af00000 {
<&mdss_dp0_phy 0>,
<&mdss_dp0_phy 1>,
<0>, <0>,
- <0>, <0>, <0>, <0>;
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <0>, <0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
