On 3/14/25 7:09 AM, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <[email protected]>
>
> Add display controller, two DSI hosts, two DSI PHYs and a single DP
> controller. Link DP to the QMP Combo PHY.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
[...]
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sar2130p-dpu";
> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
> + <0x0 0x0aeb0000 0x0 0x2008>;
size = 0x3000
[...]
> +
> + mdss_dp0: displayport-controller@ae90000 {
> + compatible = "qcom,sar2130p-dp",
> + "qcom,sm8350-dp";
> + reg = <0x0 0xae90000 0x0 0x200>,
> + <0x0 0xae90200 0x0 0x200>,
> + <0x0 0xae90400 0x0 0xc00>,
> + <0x0 0xae91000 0x0 0x400>,
> + <0x0 0xae91400 0x0 0x400>;
> + interrupt-parent = <&mdss>;
> + interrupts = <12>;
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc
> DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc
> DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_dp_qmpphy
> QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_dp_qmpphy
> QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp0_in: endpoint {
> + remote-endpoint =
> <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp0_out: endpoint {
> + remote-endpoint =
> <&usb_dp_qmpphy_dp_in>;
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-162000000 {
> + opp-hz = /bits/ 64 <162000000>;
> + required-opps =
> <&rpmhpd_opp_low_svs_d1>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps =
> <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps =
> <&rpmhpd_opp_svs_l1>;
> + };
Weirdly enough the 540 rate isn't in the clock plan for the pclk
and so isn't 162
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps =
> <&rpmhpd_opp_nom>;
> + };
> + };
> + };
[...]
> + assigned-clocks = <&dispcc
> DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc
> DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dsi0_phy 0>,
> + <&mdss_dsi0_phy 1>;
Krzysztof recently introduced defines for these
Konrad
