I am not sure if it works with latest ... I've worked it out to make a bitstream with 2019.2 which I had installed. As summary (for 2019.2) the DRAM config needs a new parameter. Also .sysdef is gone ...
Here is my diff: --- a/hardware/xilinx/scripts/vivado.tcl +++ b/hardware/xilinx/scripts/vivado.tcl @@ -16,15 +16,15 @@ # under the License. # Check if script is running in correct Vivado version. -set scripts_vivado_version 2018.3 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \ - <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado."} - return 1 -} +#set scripts_vivado_version 2018.3 +#set current_vivado_version [version -short] +# +#if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { +# puts "" +# catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \ +# <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado."} +# return 1 +#} # Parse argument list, derive the clock to utilize if { [llength $argv] eq 2 } { @@ -111,6 +111,7 @@ proc init_fifo_property {fifo width_bytes depth} { # Procedure to initialize BRAM proc init_bram_property {bram width depth} { set_property -dict [ list \ + CONFIG.use_bram_block {Stand_Alone} \ CONFIG.Assume_Synchronous_Clk {true} \ CONFIG.Byte_Size {8} \ CONFIG.Enable_32bit_Address {true} \ @@ -427,9 +428,14 @@ wait_on_run impl_1 # Export hardware description file and bitstream files to export/ dir if {[file exist $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.bit]} { + + write_hw_platform -fixed -unified -include_bit $proj_path/$proj_name.runs/impl_1/${proj_name}.xsa + file mkdir $proj_path/export - file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.sysdef \ - $proj_path/export/vta.hdf + #file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.sysdef \ + # $proj_path/export/vta.hdf + file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}.xsa \ + $proj_path/export/vta.xsa file copy -force $proj_path/$proj_name.runs/impl_1/${proj_name}_wrapper.bit \ $proj_path/export/vta.bit } I don't know exactly where .sysdef is used and/or the flow needs other updates (systef -> xsa). I've tried to look but did not spend a lot of time since it worked as is ;) The bitstream is done and it seems to be functional. Hope this helps, Mihai --- [Visit Topic](https://discuss.tvm.ai/t/vta-when-can-i-make-vta-bitstream-file-with-hls-blackbox/7651/4) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.ai/email/unsubscribe/e430eda16a31b86689657ad154f1eb5a80f2e2d42313dc5767c4564d195bd2dc).